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Integrated Circuit Systems, Inc.
ICS954119 Advance Information
Programmable Timing Control HubTM for Next Gen P4TM processor
Recommended Application: CK410 compliant clock Output Features: * 2 - 0.7V current-mode differential CPU pairs * 1 - 0.7V current-mode differential SRC pair * 6 - PCI (33MHz) * 3 - PCICLK_F, (33MHz) free-running * 1 - USB, 48MHz * 1 - 24/48 MHz * 1 - DOT, 96MHz, 0.7V current differential pair * 2 - REF, 14.318MHz * 5 - PCI-Express 0.7V current differential pairs Key Specifications: * CPU/SRC outputs cycle-cycle jitter < 85ps * PCI outputs cycle-cycle jitter < 250ps * +/- 300ppm frequency accuracy on CPU & SRC clocks Functionality
Bit2 Bit1 Bit0 CPU PCIEX SRC Bit4 Bit3 FSLC FSLB FSLA MHz MHz MHz 266.66 100.00 100.00 0 0 0 0 0 133.33 100.00 100.00 0 0 0 0 1 0 0 0 1 0 200.00 100.00 100.00 166.66 100.00 100.00 0 0 0 1 1 0 0 1 0 0 333.33 100.00 100.00 100.00 100.00 100.00 0 0 1 0 1 0 0 1 1 0 400.00 100.00 100.00 200.00 100.00 100.00 0 0 1 1 1 266.66 133.33 133.33 0 1 0 0 0 133.33 133.33 133.33 0 1 0 0 1 200.00 133.33 133.33 0 1 0 1 0 166.66 125.00 125.00 0 1 0 1 1 333.33 125.00 125.00 0 1 1 0 0 100.00 133.33 133.33 0 1 1 0 1 400.00 133.33 133.33 0 1 1 1 0 200.00 133.33 133.33 0 1 1 1 1 1 0 0 0 0 269.33 101.00 101.00 1 0 0 0 1 134.66 101.00 101.00 1 0 0 1 0 202.00 101.00 101.00 1 0 0 1 1 168.33 101.00 101.00 1 0 1 0 0 274.66 103.00 103.00 1 0 1 0 1 137.33 103.00 103.00 1 0 1 1 0 206.00 103.00 103.00 1 0 1 1 1 171.66 103.00 103.00 1 1 0 0 0 279.99 105.00 105.00 1 1 0 0 1 140.00 105.00 105.00 1 1 0 1 0 210.00 105.00 105.00 1 1 0 1 1 174.99 105.00 105.00 1 1 1 0 0 287.99 108.00 108.00 1 1 1 0 1 144.00 108.00 108.00 1 1 1 1 0 216.00 108.00 108.00 1 1 1 1 1 179.99 108.00 108.00 * Entries 00111 & 01111 are 250MHz on the B & C revision.
0875--05/24/04
Features/Benefits: * Programmable output frequencies * Programmable output skew. * Programmable spread percentage for EMI control. * Programmable watch dog safe frequency. * Supports tight ppm accuracy clocks for Serial-ATA * Supports spread spectrum modulation, 0 to -0.5% down spread, 0.25% center spread, and 0.3% center spread * * Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning Supports undriven differential CPU, SRC pair in PD# for power management.
Pin Configuration
PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.67 33.67 33.67 33.67 34.33 34.33 34.33 34.33 35.00 35.00 35.00 35.00 36.00 36.00 36.00 36.00
GND PCICLK3 PCICLK4 PCICLK5 GND VDDPCI PCICLK_F0 FSLA/PCICLK_F1 FSLB/PCICLK_F2 VDD48 **SEL24_48#/24_48MHz USB_48MHz GND DOTT_ 96MHz DOTC_96MHz Vtt_PwrGd#/PD PCIEXT0 PCIEXC0 VDDPCIEX GND PCIEXT1 PCIEXC1 PCIEXT2 PCIEXC2 GND SRCCLKT SRCCLKC VDDSRC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
VDDPCI PCICLK2 PCICLK1 PCICLK0 Reset# REF0/FSLC REF1 GND X1 X2 VDDREF SCLK SDATA CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1 CPUCLKC1 GND IREF GNDA VDDA VDDPCIEX PCIEXT4 PCIEXC4 PCIEXT3 PCIEXC3 GND
56-Pin SSOP
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICS954119
Integrated Circuit Systems, Inc.
ICS954119 Advance Information
Pin Description
PIN # PIN NAME 1 2 3 4 5 6 7 8 GND PCICLK3 PCICLK4 PCICLK5 GND VDDPCI PCICLK_F0 FSLA/PCICLK_F1 PIN TYPE PWR OUT OUT OUT PWR PWR OUT I/O DESCRIPTION Ground pin. PCI clock output. PCI clock output. PCI clock output. Ground pin. Power supply for PCI clocks, nominal 3.3V Free running PCI clock not affected by PCI_STOP# . 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / 3.3V PCI free running clock output. 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values./ 3.3V PCI free running clock output. Power pin for the 48MHz output.3.3V Latched select input for 24/48MHz output / 24/48MHz clock output. 1=24MHz, 0 = 48MHz. 48.00MHz USB clock Ground pin. True clock of differential pair for 96.00MHz DOT clock. Complement clock of differential pair for 96.00MHz DOT clock. Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. Power supply for PCI Express clocks, nominal 3.3V Ground pin. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. Ground pin. True clock of differential pair for S-ATA support. +/- 300ppm accuracy required. Complement clock of differential pair for S-ATA support. +/- 300ppm accuracy required. Supply for SRC clocks, 3.3V nominal
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
FSLB/PCICLK_F2 VDD48 **SEL24_48#/24_48MHz USB_48MHz GND DOTT_ 96MHz DOTC_96MHz Vtt_PwrGd#/PD PCIEXT0 PCIEXC0 VDDPCIEX GND PCIEXT1 PCIEXC1 PCIEXT2 PCIEXC2 GND SRCCLKT SRCCLKC VDDSRC
I/O PWR I/O OUT PWR OUT OUT IN OUT OUT PWR PWR OUT OUT OUT OUT PWR OUT OUT PWR
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2
Integrated Circuit Systems, Inc.
ICS954119 Advance Information
Pin Description
PIN # PIN NAME 29 30 31 32 33 34 35 GND PCIEXC3 PCIEXT3 PCIEXC4 PCIEXT4 VDDPCIEX VDDA TYPE PWR OUT OUT OUT OUT PWR PWR DESCRIPTION Ground pin. Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. True clock of differential PCI_Express pair. Power supply for PCI Express clocks, nominal 3.3V 3.3V power for the PLL core.
36
GNDA
PWR
Ground pin for the PLL core. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Ground pin. Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Complimentary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Data pin for SMBus circuitry, 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant. Ref, XTAL power supply, nominal 3.3V Crystal output, Nominally 14.318MHz Crystal input, Nominally 14.318MHz. Ground pin. 14.318 MHz reference clock. 14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is active low. PCI clock output. PCI clock output. PCI clock output. Power supply for PCI clocks, nominal 3.3V
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
IREF GND CPUCLKC1 CPUCLKT1 VDDCPU CPUCLKC0 CPUCLKT0 SDATA SCLK VDDREF X2 X1 GND REF1 REF0/FSLC
OUT PWR OUT OUT PWR OUT OUT I/O IN PWR OUT IN PWR OUT I/O
52 53 54 55 56
Reset# PCICLK0 PCICLK1 PCICLK2 VDDPCI
OUT OUT OUT OUT PWR
0875--05/24/04
3
Integrated Circuit Systems, Inc.
ICS954119 Advance Information
General Description
ICS954119 follows Intel CK410 Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS954119 is driven with a 14.318MHz crystal.
Block Diagram
24/48MHz 48MHz, USB PLL2 Frequency Dividers DOTT_96MHz DOTC_96MHz X1 X2 XTAL REF (1:0) CPUCLKT (1:0) CPUCLKC (1:0) Programmable Spread PLL1 Control Logic Programmable Frequency Dividers STOP Logic SRCCLKT SRCCLKC PCICLK (5:0) PCICLKF (2:0) PCI-Express (4:0) Reset# I REF
SCLK SDATA Vtt_PWRGD#/PD FSLA FSLB FSLC Sel24/48
Power Busing
VDD
6,56 10 19,34 28 35 41 46
GND
1,5 13 20,29 25 36 38 49
Description
PCI pads and Prepad
USB _48M Hz, DOT_96M Hz, Fix P LL
Differnetial PCIEX pair Differnetial SRC pair Analog Core, CPU PLL Differnetial CPU pair Xtal, Ref, CPU PLL Digital
0875--05/24/04
4
Integrated Circuit Systems, Inc.
ICS954119 Advance Information
General I2C serial interface information for the ICS954119 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
0875--05/24/04
5
Integrated Circuit Systems, Inc.
ICS954119 Advance Information
Table1: Frequency Selection Table
Bit4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit2 Bit1 Bit0 Bit3 FSLC FSLB FSLA 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 266.66 133.33 200.00 166.66 333.33 100.00 400.00 200.00 266.66 133.33 200.00 166.66 333.33 100.00 400.00 200.00 269.33 134.66 202.00 168.33 274.66 137.33 206.00 171.66 279.99 140.00 210.00 174.99 287.99 144.00 216.00 179.99 PCIEX MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 133.33 133.33 133.33 125.00 125.00 133.33 133.33 133.33 101.00 101.00 101.00 101.00 103.00 103.00 103.00 103.00 105.00 105.00 105.00 105.00 108.00 108.00 108.00 108.00 SRC MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 133.33 133.33 133.33 125.00 125.00 133.33 133.33 133.33 101.00 101.00 101.00 101.00 103.00 103.00 103.00 103.00 105.00 105.00 105.00 105.00 108.00 108.00 108.00 108.00 PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.67 33.67 33.67 33.67 34.33 34.33 34.33 34.33 35.00 35.00 35.00 35.00 36.00 36.00 36.00 36.00 Spread %
0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down 0 to -0.5% Down +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.25% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center +/-0.3% Center
0875--05/24/04
6
Integrated Circuit Systems, Inc.
ICS954119 Advance Information
I2C Table: Frequency Select Register Byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name FS Source SS_EN1 Reserved Bit4 Bit3 FSLC FSLB FSLA Control Function Frequency H/W IIC Select PLL1 Spread Enable Reserved Freq Select Bit 4 Freq Select Bit 3 Freq Select Bit 2 Freq Select Bit 1 Freq Select Bit 0 Type RW RW RW RW RW RW RW RW See Table 1: PLL 1 Frequency Selection Table 0 Latch Inputs OFF 1 IIC ON PWD 0 1 1 0 0 Latch Latch Latch
I2C Table: Output Control Register Byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 7 14,15 12 51 50 40,39 43,42 Pin # Name PCICLK_F0 DOTT/C_96MHz USB_48MHz REF0 REF1 CPUCLKT/C1 CPUCLKT/C0 CPUCLK's Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control PD Mode Output State Control Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable Driven 1 Enable Enable Enable Enable Enable Enable Enable Hi-Z PWD 1 1 1 1 1 1 1 0
I2C Table: Output Control Register Byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 4 3 2 55 54 53 9 8 Pin # Name PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 PCICLK_F2 PCICLK_F1 Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1
I2C Table: Output Control Register Byte 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 33,32 31,30 27,26 24,23 22,21 18,17 Pin # Name PCIEXCLK's Reserved PCIEXCLKT/C4 PCIEXCLKT/C3 SRCCLKT/C PCIEXCLKT/C2 PCIEXCLKT/C1 PCIEXCLKT/C0 Control Function PD Mode Output State Control Reserved Output Control Output Control Output Control Output Control Output Control Output Control Type RW RW RW RW RW RW RW RW 0 Driven Disable Disable Disable Disable Disable Disable 1 Hi-Z Enable Enable Enable Enable Enable Enable PWD 0 1 1 1 1 1 1 1
I2C Table: Output Control Register Byte 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name PCI/SRC Stop EN PCICLK_F2 PCICLK_F1 PCICLK_F0 PCIEXCLKT/C (5:3) SRCCLKT/C PCIEXCLKT/C (2:0) Reserved Control Function Stop all PCI / PCIEX / SRC clocks Stop Control Stop Control Stop Control Stop Control Stop Control Stop Control Reserved Type 0 Enable RW RW RW RW RW RW RW Free Running Free Running Free Running Free Running Free Running Free Running 1 Disable Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable PWD 1 0 0 0 1 1 1 1
0875--05/24/04
7
Integrated Circuit Systems, Inc.
ICS954119 Advance Information
I2C Table: Programmable Skew Control Register Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name PCISkw3 PCISkw2 PCISkw1 PCISkw0 ASYNC1 ASYNC0 REF0 Reserved PCI Async Freq REF0 select Reserved CPU-PCI 7 Steps Skew Control (ps) Control Function Type RW RW RW RW RW RW RW RW 0000:0 0001:N/A 0010:N/A 0011:N/A 0 0100:150 0101:N/A 0110:N/A 0111:N/A 00 = PLL1 01 = 33.0 XTAL 1000:300 1001:N/A 1010:N/A 1011:N/A 1 1100:450 1101:600 1110:750 1111:900 PWD 0 0 0 0 0 0 0 0
10 = 37.7 11 = 44.0 Fixed PLL -
I2C Table: Output Drive Control Register Byte 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Control Function Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 PWD 1 1 1 1 0 1 0 1
I2C Table: Vendor ID Register Byte 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved Reserved Reserved Reserved VID3 VID2 VID1 VID0 VENDOR ID Control Function Reserved Reserved Reserved Reserved Type RW RW RW RW R R R R 0 001 = ICS 1 PWD 0 0 0 0 0 0 0 1
I2C Table: Byte Count Register Byte 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Byte Count Programming b(7:0) Control Function Type RW RW RW RW RW RW RW RW Writing to this register will configure how many bytes will be read back, default is 0F = 15 bytes. 0 1 PWD 0 0 0 0 1 1 1 1
I2C Table: WD Time Control Register Byte 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name WD_EN WD_SEL WD Hard Status WD Soft Status WDTCtrl WD2 WD1 WD0 Control Function Watchdog Alarm Enable Watchdog Hard/Soft Alarm Select WD Hard Alarm Status WD Soft Alarm Status Watch Dog Time base Control WD Timer Bit 2 WD Timer Bit 1 WD Timer Bit 0 Type RW RW R R RW RW RW RW 0 Disable Hard only Normal Normal 290ms Base 1 Enable Hard and Soft Alarm Alarm 1160ms Base PWD 0 0 X X 0 1 1 1
These bits represent X*290ms (or 1.16S) the watchdog timer waits before it goes to alarm mode. Default is 7 X 290ms = 2s.
0875--05/24/04
8
Integrated Circuit Systems, Inc.
ICS954119 Advance Information
I2C Table: M/N Programming & WD Safe Frequency Control Register Byte 10 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name M/N_EN Reserved WD Safe Freq Source WD SF4 WD SF3 WD SF2 WD SF1 WD SF0 Watch Dog Safe Freq Programming bits Control Function PLL1 M/N Programming Enable Reserved WD Safe Freq Source Type RW RW RW RW RW RW RW RW Writing to these bit will configure the safe frequency as Byte0 bit (4:0). 0 Disable B10b(4:0) 1 Enable Latch Inputs PWD 0 0 0 0 0 0 0 0
I2C Table: PLL1 Frequency Control Register Byte 11 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name N Div8 N Div9 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 M Divider Programming bit (5:0) Control Function N Divider Prog bit 8 N Divider Prog bit 9 Type RW RW RW RW RW RW RW RW The decimal representation of M and N Divier in Byte 11 and 12 will configure the PLL1 VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] 0 1 PWD X X X X X X X X
I2C Table: PLL1 Frequency Control Register Byte 12 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 N Divider Programming Byte12 bit(7:0) and Byte11 bit(7:6) Control Function Type RW RW RW RW RW RW RW RW The decimal representation of M and N Divier in Byte 11 and 12 will configure the PLL1 VCO frequency. Default at power up = latch-in or Byte 0 Rom table. VCO Frequency = 14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2] 0 1 PWD X X X X X X X X
I2C Table: PLL1 Spread Spectrum Control Register Byte 13 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 Spread Spectrum Programming bit(7:0) Control Function Type RW RW RW RW RW RW RW RW These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage of PLL1 0 1 PWD X X X X X X X X
I2C Table: PLL1 Spread Spectrum Control Register Byte 14 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Spread Spectrum Programming bit(14:8) Control Function Reserved Type R RW RW RW RW RW RW RW These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage of PLL1 0 1 PWD 0 X X X X X X X
0875--05/24/04
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Integrated Circuit Systems, Inc.
ICS954119 Advance Information
I2C Table: Reserved Register Byte 15 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW Reserved 0 1 PWD X X X X X X X X
I2C Table: Reserved Register Byte 16 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Control Function Type RW RW RW RW RW RW RW RW Reserved 0 1 PWD X X X X X X X X
I2C Table: Reserved Register Byte 17 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Control Function Type RW RW RW RW RW RW RW RW Reserved 0 1 PWD X X X X X X X X
I2C Table: Reserved Register Byte 18 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Control Function Type RW RW RW RW RW RW RW RW Reserved 0 1 PWD 0 X X X X X X X
I2C Table: Programmable Output Divider Register Byte 19 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name CPUDiv3 CPUDiv2 CPUDiv1 CPUDiv0 PCIEXDiv3 PCIEXDiv2 PCIEXDiv1 PCIEXDiv0 PCIEX Divider Ratio Programming Bits CPU Divider Ratio Programming Bits Control Function Type RW RW RW RW RW RW RW RW 0000:/2 0001:/3 0010:/5 0011:/7 0000:/2 0001:/3 0010:/5 0011:/7 0 0100:/4 0101:/6 0110:/10 0111:/14 0100:/4 0101:/6 0110:/10 0111:/14 1000:/8 1001:/12 1010:/20 1011:/28 1000:/8 1001:/12 1010:/20 1011:/28 1 1100:/16 1101:/24 1110:/40 1111:/56 1100:/16 1101:/24 1110:/40 1111:/56 PWD X X X X X X X X
0875--05/24/04
10
Integrated Circuit Systems, Inc.
ICS954119 Advance Information
I2C Table: Programmable Output Divider Register Byte 20 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name PCIDiv3 PCIDiv2 PCIDiv1 PCIDiv0 Reserved Reserved Reserved Reserved Reserved PCI Divider Ratio Programming Bits Control Function Type RW RW RW RW RW RW RW RW 0000:/2 0001:/3 0010:/5 0011:/15 0 0100:/4 0101:/6 0110:/10 0111:/30 1000:/8 1001:/12 1010:/20 1011:/60 1 1100:/16 1101:/24 1110:/40 1111:/120 PWD X X X X X X X X
0875--05/24/04
11
Integrated Circuit Systems, Inc.
ICS954119 Advance Information
Absolute Maximum Rating
PARAMETER 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection HBM
1
SYMBOL VDD_A VDD_In Ts Tambient Tcase ESD prot
CONDITIONS -
MIN
TYP
MAX VDD + 0.5V
UNITS V V
Notes 1 1 1 1 1 1
GND - 0.5 -65 0 2000
VDD + 0.5V 150 70 115
C
C C V
Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL VIH VIL IIH IIL1 Input Low Current IIL2 Low Threshold InputHigh Voltage Low Threshold InputLow Voltage Operating Supply Current Operating Current Powerdown Current Input Frequency Pin Inductance Input Capacitance VIH_FSL VIL_FSL IDD3.3OP IDD3.3OP IDD3.3PD Fi Lpin CIN COUT CINX Clk Stabilization Modulation Frequency Tdrive_PD# Tfall_Pd# Trise_Pd# SMBus Voltage VDD TSTAB Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or deassertion of PD# to 1st clock Triangular Modulation CPU output enable after PD# de-assertion PD# fall time of PD# rise time of 2.7 CONDITIONS* 3.3 V +/-5% 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors 3.3 V +/-5% 3.3 V +/-5% Full Active, CL = Full load; all outputs driven all diff pairs driven all differential pairs tri-stated VDD = 3.3 V 14.31818 7 5 6 5 1.8 30 33 300 5 5 5.5 0.4 4 1000 300 MIN 2 VSS - 0.3 -5 -5 -200 0.7 VSS - 0.3 VDD + 0.3 0.35 350 400 70 12 TYP MAX VDD + 0.3 0.8 5 UNITS V V uA uA uA V V mA mA mA mA MHz nH pF pF pF ms kHz us ns ns V V mA ns ns Notes 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Low-level Output Voltage VOL @ IPULLUP Current sinking at IPULLUP VOL = 0.4 V SCLK/SDATA (Max VIL - 0.15) to TRI2C Clock/Data Rise Time (Min VIH + 0.15) (Min VIH + 0.15) to SCLK/SDATA TFI2C (Max VIL - 0.15) Clock/Data Fall Time *TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%
1 2
Guaranteed by design and characterization, not 100% tested in production. Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
0875--05/24/04
12
Integrated Circuit Systems, Inc.
ICS954119 Advance Information
Electrical Characteristics - CPUCLKT/C -- 0.7V Current Mode Differential Pair
PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL Zo VHigh VLow Vovs Vuds Vx(abs) d-Vx ppm Variation of crossing over all edges see Tperiod min-max values 400MHz nominal 400MHz spread 333.33MHz nominal 333.33MHz spread 266.66MHz nominal 266.66MHz spread Average period Tperiod 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread Absolute min period Tabsmin 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread Rise Time Fall Time Rise Time Variation Fall Time Variation tr tf d-tr d-tf VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V VOL = 0.175V, VOH = 0.525V CONDITIONS* VO = Vx Statistical measurement on single ended signal Measurement on single ended signal using absolute value. MIN 3000 660 -150 -300 250 550 140 -300 2.4993 2.4993 2.9991 2.9991 3.7489 3.7489 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 2.4143 2.9141 3.6639 4.8735 5.8732 7.3728 9.8720 175 175 700 700 125 125 45 55 100 150 125 85 300 2.5008 2.5133 3.0009 3.016 3.7511 3.77 5.0015 5.0266 6.0018 6.0320 7.5023 7.5400 10.0030 10.0533 850 150 1150 TYP MAX UNITS mV mV mV mV mV mV ppm ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps % ps ps ps ps NOTES 1 1,3 1,3 1 1 1 1 1,2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 1 1 1 1 1
VOH = 0.525V VOL = 0.175V Measurement from differential Duty Cycle dt3 wavefrom CPU(1:0), VT = 50% Skew tsk3 CPU(1:0) to CPU2_ITP, Skew tsk4 VT = 50% Measurement from differential Jitter, Cycle to cycle tjcyc-cyc wavefrom (CPU2_ITP) Measurement from differential Jitter, Cycle to cycle tjcyc-cyc wavefrom, (CPU(1:0)) *TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475
1 2 3
Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
0875--05/24/04
13
Integrated Circuit Systems, Inc.
ICS954119 Advance Information
Electrical Characteristics - SRC/SATA/PCIEX 0.7V Current Mode Differential Pair
PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy Average period Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation SYMBOL Zo VHigh VLow Vovs Vuds Vx(abs) d-Vx ppm Tperiod Tabsmin tr tf d-tr d-tf Variation of crossing over all edges see Tperiod min-max values 100.00MHz nominal 100.00MHz spread 100.00MHz nominal/spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V VOL = 0.175V, VOH = 0.525V CONDITIONS* VO = Vx Statistical measurement on single ended signal Measurement on single ended signal using absolute value. MIN 3000 660 -150 -300 250 550 140 -300 9.9970 9.9970 9.8720 175 175 700 700 125 125 45 55 250 125 300 10.0030 10.0533 850 150 1150 TYP MAX UNITS mV mV mV mV mV mV ppm ns ns ns ps ps ps ps % ps ps Notes 1 1,3 1,3 1 1 1 1 1,2 2 2 1,2 1 1 1 1 1 1 1
VOH = 0.525V VOL = 0.175V Measurement from differential Duty Cycle dt3 wavefrom Skew tsk3 VT = 50% Measurement from differential Jitter, Cycle to cycle tjcyc-cyc wavefrom *TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475
1 2 3
Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
Electrical Characteristics - PCICLK/PCICLK_F
PARAMETER Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Rise Time Fall Time Duty Cycle Group Skew Jitter, Cycle to cycle
1
SYMBOL RDSP VOH VOL IOH IOL tslewr/f tr tf dt1 tskew tjcyc-cyc
CONDITIONS* VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Rising/Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 12 2.4
TYP
MAX 55 0.55
UNITS V V mA mA mA mA V/ns ns ns % ps ps
NOTES 1 1 1 1 1 1 1 1 1 1 1 1 1
-33 -33 30 38 1 0.5 0.5 45 4 2 2 55 500 250
*TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7 (unless otherwise specified) Guaranteed by design and characterization, not 100% tested in production.
0875--05/24/04
14
Integrated Circuit Systems, Inc.
ICS954119 Advance Information
Electrical Characteristics - 48MHz/USB48MHz/24_48MHz
PARAMETER Long Accuracy Clock period Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Edge Rate Rise Time Fall Time Rise Time Fall Time Duty Cycle Jitter, Cycle to cycle
1
SYMBOL ppm Tperiod RDSP VOH VOL IOH IOL tslewr/f tslewr/f_USB tr tf tr_USB tf_USB dt1 tjcyc-cyc
CONDITIONS* see Tperiod min-max values 48.00MHz output nominal VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Rising/Falling edge rate USB48 Rising/Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
MIN -100 20.8313 12 2.4
TYP
MAX 100 20.8354 55 0.55
UNITS ppm ns V V mA mA mA mA V/ns V/ns ns ns ns ns % ps
NOTES 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
-33 -33 30 38 1 1 0.5 0.5 1 1 45 4 2 2 2 2 2 55 500
*TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7 (Rs is used in USB48MHz test only) Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - DOT_96MHz 0.7V Current Mode Differential Pair
PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy Average period Absolute min period Rise Time Fall Time Rise Time Variation Fall Time Variation SYMBOL Zo VHigh VLow Vovs Vuds Vx(abs) d-Vcross ppm Tperiod Tabsmin tr tf d-tr d-tf Variation of crossing over all edges see Tperiod min-max values 96.00MHz nominal 96.00MHz nominal VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V VOL = 0.175V, VOH = 0.525V CONDITIONS* VO = Vx Statistical measurement on single ended signal Measurement on single ended signal using absolute value. MIN 3000 660 -150 -300 250 550 140 -100 10.4135 10.1635 175 175 700 700 125 125 45 55 250 100 10.4198 850 150 1150 TYP MAX UNITS mV mV mV mV mV mV ppm ns ns ps ps ps ps % ps Notes 1 1,3 1,3 1 1 1 1 1,2 2 1,2 1 1 1 1 1 1
VOH = 0.525V VOL = 0.175V Measurement from differential Duty Cycle dt3 wavefrom Measurement from differential Jitter, Cycle to cycle tjcyc-cyc wavefrom *TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475
1 2 3
Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
0875--05/24/04
15
Integrated Circuit Systems, Inc.
ICS954119 Advance Information
Electrical Characteristics - REF-14.318MHz
PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Rise Time Fall Time Duty Cycle Jitter
1 2
SYMBOL ppm T period VOH VOL IOH IOL tslewr/f tr1 tf1 dt1 tjcyc-cyc
CONDITIONS see Tperiod min-max values 14.318MHz output nominal IOH = -1 mA IOL = 1 mA VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Rising/Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
MIN -300 69.8270 2.4
TYP
MAX 300 69.8550 0.4
UNITS ppm ns V V mA mA V/ns ns ns % ps
Notes 1,2 2 1 1 1 1 1 1 1 1 1
-29 29 1 1 1 45
-23 27 4 2 2 55 1000
*TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7 (Rs is used in USB48MHz test only) Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
0875--05/24/04
16
Integrated Circuit Systems, Inc.
ICS954119 Advance Information
N
c
56-Lead, 300 mil Body, 25 mil, SSOP SYMBOL
L
INDEX AREA
E1
E
12 D h x 45
A A1
A A1 b c D E E1 e h L N a VARIATIONS
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 56
D mm. MIN 18.31 MAX 18.55 MIN .720
D (inch) MAX .730
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS954119yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0875--05/24/04
17

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